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EL5825
Data Sheet June 24, 2005 FN7005.4
8-Channel TFT-LCD Reference Voltage Generator
The EL5825 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. A serial out pin enables daisy chaining of multiple devices. A number of the EL5825 can be stacked for applications requiring more than 8 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. The EL5825 has 8 outputs and is available in both the 24-pin TSSOP and the 24-pin QFN packages. It is specified for operation over the full -40C to +85C temperature range.
Features
* 8-channel reference outputs * Accuracy of 0.1% * Supply voltage of 4.5V to 16.5V * Digital supply 3.3V to 5V * Low supply current of 8mA * Rail-to-rail capability * Pb-Free plus anneal available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Reference voltage generators
Pinouts
EL5825 (24-PIN TSSOP) TOP VIEW
1 SCLK 2 SDO SDI 24 22 SDI ENA 23 OUTA 22 OSC 1 4 VSD 5 NC 6 VS 7 REFH OUTB 21 VSD 2 18 OUTC 17 OUTD Thermal Pad OUTC 20 NC 3 OUTD 19 VS 4 GND 18 REFH 5 OUTE 17 REFL 6 9 GND 10 NC 11 CAP 12 NC OUTF 16 GND 7 NC 10 NC 11 OUTH 12 CAP 8 NC 9 13 OUTG OUTG 15 OUTH 14 NC 13 14 OUTF 20 OUTA 19 OUTB 16 GND 15 OUTE 23 SCLK 24 SDO 21 ENA
EL5825 (24-PIN QFN) TOP VIEW
Ordering Information
PART NUMBER EL5825IL EL5825IL-T7 EL5825IL-T13 EL5825ILZ (See Note) EL5825ILZ-T7 (See Note) EL5825ILZ-T13 (See Note) EL5825IR EL5825IR-T7 EL5825IR-T13 EL5825IRZ (See Note) EL5825IRZ-T7 (See Note) PACKAGE 24-Pin QFN 24-Pin QFN 24-Pin QFN 24-Pin QFN (Pb-free) 24-Pin QFN (Pb-free) 24-Pin QFN (Pb-free) 24-Pin TSSOP 24-Pin TSSOP 24-Pin TSSOP 24-Pin TSSOP (Pb-free) 24-Pin TSSOP (Pb-free) TAPE & REEL PKG. DWG. # 7" 13" 7" 13" 7" 13" 7" 13" MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
3 OSC
THERMAL PAD
8 REFL
MDP0046 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044
EL5825IRZ-T13 24-Pin TSSOP (See Note) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5825
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . .+18V Supply Voltage between VSD and GND . . . . . . . VS and +7V (max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS ISD ANALOG VOL VOH ISC PSRR tD VAC VDROOP RINH REG BG DIGITAL VIH VIL FCLK tS tH tLC tCE tDCO RSDIN Supply Current
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
No load
7.6 0.17
9 0.35
mA mA
Digital Supply Current
Output Swing Low Output Swing High Short Circuit Current Power Supply Rejection Ratio Program to Out Delay Accuracy Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation Band Gap
Sinking 5mA (VREFH = 15V, VREFL = 0) Sourcing 5mA (VREFH = 15V, VREFL = 0) RL = 10 VS+ is moved from 14V to 16V 14.85 100 45
50 14.95 140 60 4 20 1 34
150
mV V mA dB ms mV
2
mV/ms k
IOUT = 5mA step 1.1
0.5 1.3
1.5 1.6
mV/mA V
Logic 1 Input Voltage Logic 0 Input Voltage Clock Frequency Setup Time Hold Time Load to Clock Time Clock to Load Line Clock to Out Delay Time SDIN Input Resistance Negative edge of SCLK
VSD20% 20%* VSD 5 20 20 20 20 10 1
V V MHz ns ns ns ns ns G
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FN7005.4 June 24, 2005
EL5825 Pin Descriptions
24-PIN QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 24-PIN TSSOP 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 PIN NAME OSC VSD NC VS REFH REFL GND CAP NC NC NC OUTH OUTG OUTF OUTE GND OUTD OUTC OUTB OUTA ENA SDI SCLK SDO Analog Output Analog Output Analog Output Analog Output Power Analog Output Analog Output Analog Output Analog Output Logic Input Logic Input Logic Input Logic Output Power Analog Input Analog Input Power Analog PIN TYPE IP/OP Power PIN DESCRIPTION Oscillator pin for synchronizing multiple chips Positive power supply for digital circuits (3.3V - 5V) Not connected Positive supply voltage for analog circuits High reference voltage Low reference voltage Ground Decoupling capacitor for internal reference generator, 0.1F Not connected Not connected Not connected Channel H programmable output voltage Channel G programmable output voltage Channel F programmable output voltage Channel E programmable output voltage Ground Channel D programmable output voltage Channel C programmable output voltage Channel B programmable output voltage Channel A programmable output voltage Chip select, low enables data input to logic Serial data input Serial data clock Serial data output
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EL5825 Typical Performance Curves
INPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 0.3 0.2 0.1 ISD (nA) 0 -0.1 -0.2 -0.3 10 180 160 140 120 100 80 60 VS=15V VSD=5V VREFH=13V VREFL=2V 210 410 610 810 1010 40 20 0 3 3.5 4 4.5 5 5.5 VSD (V)
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE
7.2 7 6.8 6.6 IS (mA) 6.4 6.2 6 5.8 5.6 4 6 8 VOUT=0V
VS (V)
VS=VREFH=15V M=400ns/DIV 0mA 5mA CL=4.7nF RS=20 5V CL=1nF RS=20 CL=180pF 200mV/DIV 5mA/DIV
10
12
14
16
18
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
VS=VREFH=15V M=400ns/DIV
M=200s/DIV
5mA SCLK 0mA CL=1nF RS=20 SDA ENA CL=4.7nF RS=20 CL=180pF
OUTA
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
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EL5825 Typical Performance Curves
(Continued)
M=200s/div
SCLK
SDA ENA
OUTA
FIGURE 7. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 781mW
TS SO P2 =1 4 28 C /W
1.176W
TS
0.8 0.6 0.4 0.2 0 0 25
JA =
SO P2 4 85 C /W
JA
50
75 85
100
125
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 0.7 POWER DISSIPATION (W)
3
POWER DISSIPATION (W)
2.5 2 1.5 1 0.5
0 0
2.703W
Q FN JA 24 =3 7 C /W
0.6 0.5 0.4 0.3 0.2 0.1 0 0
714mW
Q J
24 /W FN C 40 =1
A
25
50
75 85 100
125
150
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7005.4 June 24, 2005
EL5825 Product Description
The EL5825 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5825, this curve can be changed to optimize its characteristics according to the required application of the display product. Each of the reference voltage outputs can be set with a 10-bit resolution. These outputs are available to within 100mV of the power rails of the EL5825. As all of the output buffers are identical, it is also possible to use the EL5825 for applications other than LCDs where 8 voltage references are required that can be set to a 10-bit accuracy. allocated to the following functions (also refer to the Control Bits Logic Table) * Bit 15 is always set to a zero * Bit 14 controls the source of the clock, see the next section for details * Bits 13 through 10 select the channel to be written to, these are binary coded with channel A = 0, and channel H=7 * The 10-bit data is on bits 9 through 0. Some examples of data words are shown in the table of Serial Programming Examples
TABLE 1. CONTROL BITS LOGIC TABLE BIT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 NAME Test Oscillator A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Always 0 0 = Internal, 1 = External Channel Address (don't care) Channel Address Channel Address Channel Address Data Data Data Data Data Data Data Data Data Data DESCRIPTION
Serial Interface
The EL5825 is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. To facilitate the system designs that use multiple EL5825 chips, a buffered serial output of the shift register (SDO pin) is available. Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. To control the multiple EL5825 chips from a single three-wire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next chip. While the ENA is held low, the 16m-bit data is loaded to the SDI input of the first chip. The first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. While the ENA is held high, all addressed outputs will be updated simultaneously. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are
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EL5825 Serial Timing Diagram
ENA
tHE
tSE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B15 MSB
B14
B13
B12-B2
B1
B0 t LSB
Load MSB first, LSB last
TABLE 2. SERIAL TIMING PARAMETERS PARAMETER T tr/tf tHE tSE tHD tSD tW EXAMPLE 200ns 0.05 * T 10ns 10ns 10ns 10ns 0.50 * T DESCRIPTION Clock Period Clock Rise/Fall Time ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width TABLE 3. SERIAL PROGRAMMING EXAMPLES CONTROL C1 0 0 0 0 0 0 C0 0 0 0 0 0 1 CHANNEL ADDRESS A3 X X X X X X A2 0 0 0 0 1 1 A1 0 0 0 1 1 1 A0 0 0 0 1 1 1 D9 0 1 1 1 0 0 D8 0 1 0 0 0 0 D7 0 1 0 0 0 0 D6 0 1 0 0 0 0 DATA D5 0 1 0 0 0 0 D4 0 1 0 0 1 1 D3 0 1 0 0 1 1 D2 0 1 0 0 1 1 D1 0 1 0 0 1 1 D0 0 1 0 1 1 1 CONDITION Internal Oscillator, Channel A, Value = 0 Internal Oscillator, Channel A, Value = 1023 Internal Oscillator, Channel A, Value = 512 Internal Oscillator, Channel C, Value = 513 Internal Oscillator, Channel H, Value = 31 External Oscillator, Channel H, Value = 31
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FN7005.4 June 24, 2005
EL5825
Internal Refresh Clock Oscillator
The EL5825 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 25kHz and can be output to the OSC pin. In a multiple chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. Subsequent chips may have the OSC pin connected to this clock source. In these chips, the program will set them to external OSC Mode by setting bit 14 to 1. See the control bits logic table and serial programming example for details. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing on page 10 shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. After programming the oscillator with bit 14, the pin will be set to the appropriate mode.
Transfer Function
The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 1024
where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5825 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5825. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 8 channels, the system can be designed such that one EL5825 will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5825 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing on page 10 shows a system connected in this way.
Block Diagram
REFERENCE HIGH
OUTA
OUTB
OUTC
OUTD EIGHT CHANNEL REGISTERS VOLTAGE SOURCES
OUTE
OUTF
OUTG
OUTH
REFERENCE LOW CAP SERIAL DATA INPUT SERIAL CLOCK CONTROL IF ENABLE SERIAL DATA OUTPUT
OSCILLATOR INPUT/OUTPUT3
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EL5825
Channel Outputs
Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 100mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 40s. In the worst-case scenario this will be 320s, when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2 volt steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16 volts can take between 2.56 milliseconds and 3 milliseconds depending on the absolute timing relative to the update cycle. Where: * i = 1 to total 8 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, We can solve for the RLOAD's to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat.
Power Supply Bypassing and Printed Circuit Board Layout
Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5825. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5825 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins.
Power Dissipation
With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
Application Using the EL5825
In the application drawing, the schematic shows the interconnect of a pair of EL5825 chips connected to give 8 gamma corrected voltages above the VCOM voltage, and 8 gamma corrected voltages below the VCOM voltage. By using the serial data out pin, it is possible to daisy chain (cascade) the two chips. In this mode the micro-controller will send a 32-bit word that will update both the upper and lower references voltages in one operation. See Application Drawing 1 for details.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
when sinking. 9
FN7005.4 June 24, 2005
EL5825 Application Drawing
HIGH REFERENCE VOLTAGE +10V 0.1F +12V 0.1F MICROCONTROLLER +5V 0.1F SERIAL DATA SERIAL DATA CLOCK ENABLE SERIAL DATA SDO HORIZONTAL RATE 0.1F REFL GND OUTH OSC CAP OUT OUTF OUTD VSD OUTC LCD PANEL VS OUTB
EL5825 REFH OUTA COLUMN (SOURCE) DRIVER
SDI SCLK
OUTE ENA
LCD TIMING CONTROLLER
+5.5V
MIDDLE REFERENCE VOLTAGE
REFH OSC +12V 0.1F +5V 0.1F SERIAL DATA SERIAL DATA CLOCK SCLK ENABLE ENA CAP LOW REFERENCE VOLTAGE +1V 0.1F GND 0.1F SDI VSD VS
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
REFL
OUT
OUTH
Serial Timing Diagram (32 bit)
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FN7005.4 June 24, 2005
EL5825 QFN Package Outline Drawing
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FN7005.4 June 24, 2005
EL5825 TSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7005.4 June 24, 2005

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